Dauug|36 present status

The architecture is not ready for you to build yet.

What works now

An electrical simulation of the circuit board works for some 190 opcodes.
The anticipated CPU speed is 10 MIPS across −40 °C to +85 °C.
Paged virtual memory and preemptive multitasking work correctly.
Paravirtualized I/O is available via the simulation.
A boot loader, several sample programs, and dozens of regression tests work.
An operating system kernel is written, working, and documented.
Portions of the Dauug|18 subarchitecture also work. More information is here.

The CPU has been simulated at 16.729 MIPS, but under unrealistic signal integrity assumptions. SPICE modeling of reflection scenarios has us optimistic that the CPU will be usable to 10 MIPS.

Next steps

Finish the Dauug|18 subarchitecture for use in the firmware loader and I/O subsystem.
Complete the design of and simulate the firmware loader.
Complete the design of and simulate I/O subsystem.
Finalize circuit board (routing, bypass capacitors, connectors, etc.).
Plot board.
Mount components.
Does it work?

Our team’s status

Information about us is online at dauug.org.

This page created

23 April 2025.